The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, the present invention relates to a switching circuit utilizing a high voltage transistor protection technique for integrated circuit devices having dual voltage supplies.
In certain integrated circuit devices (e.g. some memory ICs) a high voltage supply level (xe2x80x9cVCCPxe2x80x9d) may be required for proper device operation. Should this voltage be equal to or less than twice the supply voltage (xe2x80x9cVCCxe2x80x9d, i.e. VCCPxe2x89xa62*VCC ), then a switching circuit comprising a relatively thick gate oxide P-channel transistor in series with a pair of series connected N-channel transistors may be coupled between VCCP and a reference voltage level (VSS or circuit ground) with the gate of the P-channel device coupled to a switched source of VCCP, the gate of the intermediate N-channel device coupled to VCC and the gate of the remaining N-channel device coupled to a switched source of VCC.
However, in those applications wherein the high voltage supply level is more than twice the device supply voltage (i.e. VCCP greater than 2*VCC) and relatively thick gate oxide thickness transistors are used, the associated thin gate oxide transistors must still be protected from possible high gate oxide voltage stress.
The switching circuit incorporating a high voltage transistor protection technique of the present invention extends the maximum pumped voltage (xe2x80x9cVCCPxe2x80x9d) for reliable MOS transistor operation to VCCP=VTN+(2*VCC). This is effectuated by adding an additional relatively thick gate oxide transistor in series with the thin gate oxide MOS N-channel transistors in a conventional high voltage switching circuit to increase the reliable maximum voltage for the high voltage power supply.
Particularly disclosed herein is an integrated circuit device including a switching circuit comprising first and second series coupled MOS transistors having a gate oxide of a first thickness, each of the first and second MOS transistors having a gate terminal thereof. Third and fourth MOS series coupled transistors are also provided having a gate oxide of a second thickness lesser than the first thickness, each of the third and fourth MOS transistors having a gate terminal thereof. The first, second, third and fourth MOS transistors are coupled in series between a high voltage source and a reference voltage source with an output node defined intermediate the first and second MOS transistors. A first signal input is coupled to the gate terminal of the first transistor for receiving a first input signal capable of transitioning between a level of the high voltage source and a level of the reference voltage source with the gate terminal of the second transistor being coupled to the high voltage source. A supply voltage source having a voltage level lesser than that of the high voltage source is coupled to the gate terminal of the third transistor. A second signal input is coupled to the gate terminal of the fourth transistor for receiving a second input signal capable of transitioning between a level of the supply voltage source and a level of the reference voltage source.